Latency improvements for the Vmicro16 SoC by clustering cores into multiple groups and using multiple-level interconnects.
Multi-core RISC SoC with various peripherals including: watchdogs, timer interrupts, GPIO, UART, and more.
16-bit RISC processor design and implementation for Xilinx Spartan-6 FPGAs featuring pipelining, on-chip memory, GPIO, and UART modules.
A 2-layer board for the Minispartan6+ FPGA development kit. Features an STM32F0 TSSOP processor, mutliple power supplies, I2C, ICSP, and LEDs.
Compiler and assembler for the PRCO embedded processor. Features simple optimisations including constant folding and unreachable code elimination.
Designed, implemented, and evaluated a parallel implementation of the Discrete Fourier Transform.
Read the methodology and results here.
A dynamic object-oriented programming language, compiler, and virtual machine, implemented in C.
Verilog, SystemVerilog, FPGA, CPU uarch, ASIC flows, Formal verification, UVM, AMBA